A PALplus-Compatible HDTV Encoder System
نویسندگان
چکیده
This paper presents a new implementation for realising PALplus signals from High-Definition Television (HDTV) transmissions. A proposed encoder design is introduced, which decomposes the HDTV input into two separate channels, the first of which subsamples the input signal to produce the standard resolution TV signal, and the second derives a digitally compressed residual component. The problems of non-uniform line structure due to the decimation of an interlaced signal are addressed, as are the visible distortions caused by aliasing and cross-talk effects, with appropriate solutions presented. Finally the important issues of colour enhancement and the composition of the compatible signal are briefly discussed.
منابع مشابه
Schmidt, Dooley and Buchwald: A PALplus Compatible HDTV Encoder System A PALPLUS COMPATIBLE HDTV ENCODER SYSTEM
This paper presents a new implementation for realising PALplus signals from High-Definition Television (HDTV) transmissions. A proposed encoder design is introduced, which decomposes the HDTV input into two separate channels, the first of which subsamples the input signal to produce the standard resolution TV signal, and the second derives a digitally compressed residual component. The problems...
متن کاملOL_H264LD-CFS HDTV H.264/AVC Limited Baseline Video Decoder With Compressed Frame Store
General Description Applications Features The OL_H264LD-CFS core is a hardware implementation of the H.264 baseline video compression algorithm. The core decodes a bitstream produced by the OLH264E-CFS encoder and produces a video stream up to the highest HDTV resolution. Simple, fully synchronous design with low gate count. ♦ Digital video recorders. ♦ Video wireless devices. ♦ Video surveilla...
متن کاملFPGA Implementation and Verification System of H.264/AVC Encoder for HDTV Applications
For huge systems like video processing, FPGA prototyping plays an important role before taping out. In this paper, a verification system for H.264/AVC encoders with FPGA prototyping is proposed and implemented. An H.264 encoder with baseline profile of Level 3.2 was carried out with a clock frequency of 200MHz on a Xilinx Virtex-6 FPGA connected with DDR3 memory, which could satisfy real-time e...
متن کاملA 212MPixels/s 4096×2160p multiview video encoder chip for 3D/quad HDTV applications
A 4096×2160p multiview video encoder chip is implemented on a 3.95mm×2.90mm die with 90nm CMOS technology. A view-parallel macroblock-interleaved scheduling with 8stage macroblock pipelined architecture achieves 212Mpixels/s throughput, which is 3.4× to 7.7× better than the state-of-the-art encoder chips. In addition, 94% on-chip SRAM area and 79% external system memory bandwidth are saved.
متن کاملA 212 MPixels/s 4096 ˟ 2160p Multiview Video Encoder Chip for 3D/Quad Full HDTV Applications
Multiview video coding (MVC) plays an important role in a 3-D video system. In addition, the resolution of HDTV is increasing to present more vivid perception for users. To realize real-time processing of dozens of TOPS, VLSI solution is necessary. However, ultra high computational complexity, a large amount of external memory bandwidth and on-chip SRAM size, and complex MVC prediction structur...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2010